CPU	"F:\USER0\PROG\CROSS-32 4.0\68HC11.TBL"
	HOF	"MOT8"

NO	EQU	0D
YES	EQU	NOT NO

;************************************************************************
;									*
;                      I/O EXPANSION SUPPORT CODE			*
;									*
;                       VERSION 002 (for Buffalo)			*
;									*
;************************************************************************

;************************************************************************
;           DESCRIPTION
;************************************************************************

; This is an example of how to support the GPC_5A1 (GPC_4A5) LCD driver
;  module from the HC11 based CPU_1A1 under Buffalo.

; It works by storing commands and text messages in memory, and then
;  sending them to the LCD as required using a simple subroutine call.

; The commands and messages can be predefined and stored in Flash or
;  RAM, or can be assembled from variables as required.

; Command messages allow the LCD module to be comtrolled directly. This
;  includes clearing the display and moving the cursor to where the
;  text is to start.

; This example runs under Buffalo. The LDC driver module must be connected
;  to the CPU_1A1.
;	Int	to CPU_1A1 INT input (pin-)
;	Dat	to Port-A bit-5
;	Clk	to Port-A bit-6

; Run Buffalo. Use the command "load t" to load the .HEX file created by
;  assembling this file (supplied already assembled).
; Use the command "go 2000" to run the loaded code.
; The startup message on the LCD will change.
; Buffalo then re-starts (you can run it again).

; Examine the operation of this file to determine how to use the same
;  functions in your own applications. You can copy the code from this
;  file.

; Don't worry about the interrupt service routine included within this
;  file. It is used for reception of data from the I/O modules, but is
;  not used by this example.
; The LCD controller is treated as a write-only device.

; NOTES:
;	This file should assemble under MiniIDE. It will require
;	 modification to assemble under ASM11.
;	The ASM11 mods. are syntax based only. Refer to the ASM11 manual
;	 for details of required syntax.

;************************************************************************
;           REVISION HISTORY
;************************************************************************

; 09 Mar 2000
;  1.    Start by creating basic I/O description and operation notes.
;  2.    Cut the file back to a bare minimum of relavent code.

;************************************************************************
;************************************************************************
;									*
;               EQUATES - SYSTEM - RAM - ROM - EEPROM			*
;									*
; This section defines where the memnory is located for the assembler	*
;									*
;************************************************************************

RAMBS1		EQU	0000H		; START OF RAM BLOCK 1
RAMBS2		EQU	0100H		; START OF RAM BLOCK 2
REGBS		EQU	1000H		; START OF REGISTERS

; For this demo flash and eeprom have been moved into RAM.
; This allow this code to be loaded and run using Buffalo.

FLS_SA		EQU	2000H		; START OF FLASH
FLS_EA		EQU	7DFFH		; END OF FLASH
EEP_SA		EQU	7E00H		; START OF EEPROM
EEP_EA		EQU	7FFFH		; END OF EEPROM

;************************************************************************
;   HC11F1 REGISTERS							*
;									*
; This section defines the HC11F1 registers for the assembler		*
;									*
;************************************************************************

PORTA		EQU	00H		; PORT A
PORTA1		EQU	REGBS+00H	; PORT A
DDRA		EQU	01H		; PORT A DDR
PORTG		EQU	02H		; PORT G
DDRG		EQU	03H		; PORT G DDR
PORTB		EQU	04H		; PORT B
PORTCL		EQU	05H		; PROT C LATCHED DATA REG.
DDRC		EQU	07H		; DATA DIRECTION REGISTER C
PORTD		EQU	08H		; PORT D
PORTD1		EQU	REGBS+08H	; PORT D
DDRD		EQU	09H		; DATA DIRECTION REGISTER D
PORTE		EQU	0AH		; PORT E
CFORC		EQU	0BH		; TIMER COMPARE FORCE REG.
OC1M		EQU	0CH		; O/P COMPARE 1 MASK REG.
OC1D		EQU	0DH		; O/P COMPARE 1 DATA REG
TCNTH		EQU	0EH		; TIMER COUNT H
TCNTL		EQU	0FH		;             L
TIC1H		EQU	10H		; TIMER O/P COMPARE 1 H
TIC1L		EQU	11H		;                   1 L
TIC2H		EQU	12H		;                   2 H
TIC2L		EQU	13H		;                   2 L
TIC3H		EQU	14H		;                   3 H
TIC3L		EQU	15H		;                   3 L
TOC1H		EQU	16H		; TIMER O/P COMPARE	1 H
TOC1L		EQU	17H		;			1 L
TOC2H		EQU	18H		;			2 H
TOC2L		EQU	19H		;			2 L
TOC3H		EQU	1AH		;			3 H
TOC3L		EQU	1BH		;			3 L
TOC4H		EQU	1CH		;			4 H
TOC4L		EQU	1DH		;			4 L
TOC5H		EQU	1EH		;			5 H
TOC5L		EQU	1FH		;			5 L
TCTL1		EQU	20H		; TIMER CONTROL REG 1
TCTL2		EQU	21H		; TIMER CONTROL REG 2
TMSK1		EQU	22H		; TIMER MASK 1
TFLG1		EQU	23H		; TIMER FLAG 1
TMSK2		EQU	24H		; TIMER MASK 2
TFLG2		EQU	25H		; TIMER FLAG 2
PACTL		EQU	26H		; PULSE ACCUMULATOR CONT. REG.
PACNT		EQU	27H		; PULSE ACCUMULATOR COUNT REG.
SPCR		EQU	28H		;
SPSR		EQU	29H		;
SPDR		EQU	2AH		;
BAUD		EQU	2BH		; SCI BAUD REG
SCCR1		EQU	2CH		; SCI CONTROL 1 REG
SCCR2		EQU	2DH		; SCI CONTROL 2 REG
SCSR		EQU	2EH		; SCI STATUS REG
SCDR		EQU	2FH		; SCI DATA REG
ADCTL		EQU	30H		;
ADR1		EQU	31H		;
ADR2		EQU	32H		;
ADR3		EQU	33H		;
ADR4		EQU	34H		;
BPROT		EQU	35H		;
OPTION		EQU	39H		; OPTION REG
COPRST		EQU	3AH		; COP RESET REG
PPROG		EQU	REGBS+3BH	; EEPROM PROG REG
HPRIO		EQU	3CH		; HPRIO REG
INIT		EQU	3DH		; INIT
INITSU		EQU	103DH		; INIT AT RESET
CONFIG		EQU	3FH		; CONFIG REG
CSSTRH		EQU	5CH		; CS CYCLE STRETCH
CSCTL		EQU	5DH		; CS CONTROL
CSGADR		EQU	5EH		; GENERAL PURPOSE CS (RAM)
CSGSIZ		EQU	5FH		; GENERAL PURPOSE CS SIZE

;************************************************************************
;  CONSTANTS								*
;									*
; These are labels (definitions) that are of fixed value		*
; These define the LCD connection to the CPU_1A1			*
;									*
;************************************************************************

LED	EQU	10000000B	; LED indicator			PORT A7
EXPDATI	EQU	00100000B	; expansion data input		PORT A5
EXPCLK	EQU	01000000B	; expansion clock output	PORT A6
EXPDATO	EQU	00100000B	; expansion data output		PORT A5

UID	EQU	0F0H		; unit ID number

DDRAD	EQU	11100000B	; Port-A DDR default

;************************************************************************
;     RAM								*
;									*
; This sections defines the location of variables and buffers within	*
;  RAM.									*
;									*
;************************************************************************

; some variables required to be in zero page for bit manipulation

	ORG	RAMBS1			; start of RAM

LOGCODE		DFS	1		; reset log code (not cleared at reset)

FLAGS1		DFS	1		; GP FLAGS
EXPFLG1		DFS	1		; GP FLAGS

DEBUG		DFS	1		; debug variable
DEBUGA		DFS	1		; debug variable (last pass)

TIM1		DFS	2		; general purpose delay timer
TIM2		DFS	2		; loop delay timer

LCPS1		DFS	1		; LCP STATUS #1

;************
; buffers & control variables

	ORG	RAMBS2			; second block of RAM

EXBUF1	EQU	EXBUF1			; 32 byte TX expansion message buffer
EXB1CK	EQU	EXBUF1+31D		;   checksum temp variable

EXBUF2	EQU	EXBUF1+32D		; 32 byte RX expansion network buffer
EXB2LB	EQU	EXBUF2+29D		;   RX last byte received
EXB2BC	EQU	EXBUF2+30D		;   RX buffer offset pointer
EXB2CK	EQU	EXBUF2+31D		;   checksum temp variable

EXBUF3	EQU	EXBUF2+32D		; .

;************
; SYSTEM STACK

STACK	EQU	03FFH			; STACK POINTER (03FFh down to 0300h)

;************************************************************************
;************************************************************************
;************************************************************************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************; P R O G R A M   S T A R T S   H E R E ********************
;************************************************************************
;************************************************************************
;************************************************************************

;                   INITIALISATION & APPLICATION CODE

;************************************************************************

	ORG	FLS_SA				; start of main program

START	LDX	#REGBS				; register base address
	LDAA	#DDRAD				;
	STAA	DDRA,X				;

;************
; misc configuration

	LDAA	#10000010B			; startup default
	STAA	LCPS1				;  "
	LDAA	#00H				;
	STAA	EXPFLG1				;

;************
; delay then show reset on LCD

	LDY	#31D				;  > 0.5 seconds
	JSR	DELAY1				;  >  delay

	LDY	#IOM11				; line 1 position
	JSR	IOTXPM				;    display

	LDY	#IOM51				; line 1 message
	JSR	IOTXPM				;    display

	LDY	#IOM12				; line 2 position
	JSR	IOTXPM				;    display

	LDY	#IOM52				; line 2 message
	JSR	IOTXPM				;    display

	JMP	8000H				; return to Buffalo

;************************************************************************
;************************************************************************
;************************************************************************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;******************** I/O EXPANSION SUPPORT ROUTINES ********************
;************************************************************************
;************************************************************************
;************************************************************************

;------------------------------------------------------------------------
;------------------------------------------------------------------------
; I/O MODULE COMMUNICATIONS
;------------------------------------------------------------------------
;------------------------------------------------------------------------

; To send data out to a module, the complete message is loaded into EXBUF1 and
;  then the buffer contents transmitted. The checksum is added during
;  transmission.
; The byte count is saved to EXBUF1+3.

;	write the message out
;	release the interrupt
;	write the checksum out
;	wait for ACK

; To read data from a module:
;	write the message out
;	release the interrupt
;	write the checksum out
;	wait for the reply

;------------------------------------------------------------------------

;************
; Transmit a pre-defined message

; This is used to send messages that are stored in Memory, usually Flash.
; Often the message will be a text string to be displayed. It can also be
;  an LCD command.

; The first byte is a copy of the byte count.
; Message addressed by "Y"

IOTXPM	BSET	EXPFLG1,00010000B		; flag TX in progress
	LDX	#EXBUF1				; destination buffer base address
	LDAB	0,Y				; get the "byte count"
	DEX					; conpensate for 1st pass
					; copy message
IOTXPM1	INX					; next target address
	INY					; next source address
	LDAA	0,Y				; read data
	STAA	0,X				; save data
	DECB					; byte count -1
	BNE	IOTXPM1				;  loop
	LDX	#REGBS				; restore X
					; send now
	JSR	IOTX10				; send message now
					; finished
	RTS					; return

; example message send call

;	LDY	#IOM1				; message address
;	JSR	IOTXPM				;  send message

; example message

;IOM1	DFB	IOM1_E-IOM1-1		; byte count
;	DFB	21H			; id		KDC1
;	DFB	00H			; to		all units of ID 21
;	DFB	UID			; from		the master
;	DFB	IOM1_E-IOM1-1		; byte count
;	DFB	0D7H			; command	write data to display
;	DFB	"LCP Reset"		; data		message body
;IOM1_E	DFB	00H			; checksum

;************
; subroutines

; Send buffer EXBUF1, now

IOTX10	BSET	EXPFLG1,00010000B		; flag TX in progress
	LDY	#EXBUF1				; buffer start address
	CLR	EXB1CK				; clear checksum
	LDAA	EXBUF1+3			; read byte count
					; loop
IOTX11	LDAB	0,Y				; read data byte
	JSR	IOTX70				; send byte
	ADDB	EXB1CK				;  add to checksum
	STAB	EXB1CK				;  save
	INY					; next address
	DECA					; byte counter
	BNE	IOTX11				; loop
					; checksum
	CLRB					; zero
	SUBB	EXB1CK				; B=OO-B
	JSR	IOTX70				; send byte
					; settling time
	LDX	#3000H			; 1F00H	; \
IOTX12	DEX					;  > approx. 20mS delay
	BNE	IOTX12				; /
					; finished
	BCLR	EXPFLG1,00010000B		; clear TX in progress flag
	RTS					; return

;************
; send byte in B (MSB first)

IOTX70	LDX	#REGBS				; \  registers
	BSET	DDRA,X,EXPDATO			; |  make data line = output
	BSET	DDRA,X,EXPCLK			; |  ensure clock = ouput
	BCLR	PORTA,X,EXPCLK			; /  ensure clock is clear
	BRCLR	EXPFLG1,00001000B,IOTX70B	; continue, no recent RX
	LDX	#1F00H				; \
IOTX70A	DEX					;  > approx. 20mS delay
	BNE	IOTX70A				; /
	BCLR	EXPFLG1,00001000B		; done
	LDX	#REGBS				; restore X

IOTX70B	BSET	EXPFLG1,00010000B		; flag TX in progress
	PSHA					; save A (1)
	PSHB					; save B (2) (data)
	LDAA	#08D				; LOAD BIT COUNTER

IOTX71	ROLB					; rotate data bit through carry
	PSHB					; temp save data byte (3)
	BCC	IOTX72				; \
	BSET	PORTA,X,EXPDATO			;  > set TX data bit
	BRA	IOTX73				;  >
IOTX72	BCLR	PORTA,X,EXPDATO			; /
						;
IOTX73	LDAB	#02D			; 20	; \
IOTX74	DECB					;  > clock edge delay
	BNE	IOTX74				; /
	BSET	PORTA,X,EXPCLK			; set clock
	LDAB	#20D			; 80	; \
IOTX75	DECB					;  > bit timing delay
	BNE	IOTX75				; /
	BCLR	PORTA,X,EXPCLK			; clear clock
	PULB					; restore B (3)
	DECA					; \ bit counter
	BNE	IOTX71				; /  "
	BCLR	DDRA,X,EXPDATO			; make data line = input
	PULB					; restore B (2) (data)
	PULA					; restore A (1)
	BCLR	PORTA,X,EXPDATO			; clear TX data output
	BCLR	EXPFLG1,00010000B		; flag TX complete
	RTS					; finished

;************************************************************************
;************************************************************************
;****; INTERRUPT SERVICE ROUTINES ****; INTERRUPT SERVICE ROUTINES ******
;****; INTERRUPT SERVICE ROUTINES ****; INTERRUPT SERVICE ROUTINES ******
;************************************************************************
;************************************************************************

;------------------------------------------------------------------------
;------------------------------------------------------------------------
;                                                                       *
; IRQ   -- I/O MODULE COMMUNICATIONS (RX)                               *
;                                                                       *
;------------------------------------------------------------------------

; This routine communicates with the newer I/O expansion modules on the
;  LCP_2A* board.

; The number of bytes to be received is obtained from the message being
;  received (EXBUF2+3).
; At the start of reception, the byte count is set to FF bytes which is
;  larger than any practical message. As soon as the byte count is received,
;  it is adjusted (-3) and used to complete the message (EXB2BC).

; Flags indicate the result:
;	expflg1,10000000 = set if reception complete
;	expflg1,01000000 = set if reception checksum error
;	expflg1,00100000 = set if other reception error
;	expflg1,00010000 = set if a TX is in progress

; The Interrupt is asserted by each slave when receiving a message being
;  sent by the master. This prevents slaves not receiving the message
;  from transmitting during the message.
; The flags "expflg1,00010000" is set by the master transmission routine to
;  prevent the master IRQ reception on this interrupt. It also prevents
;  polling during a transmission in progress.

; The data line is sampled on the falling edge of the CLOCK.

; For message structure & other details see the TX section description.

;------------------------------------------------------------------------

; Receive a message

; This receives a message from a slave device, storing it in a RAM buffer.


;************
; receive message (MSB first)

IRQ	BRCLR	LCPS1,00100000B,IRQRX79		; skip for now (disabled)
	RTI					;  return quickly

IRQRX79	BRCLR	EXPFLG1,00010000B,IRQRX70	; process RX
	RTI					;  TX in progress, no RX required

IRQRX70	CLI					; allow other interrupts
	PSHX					; save X
	PSHA					; save A
	PSHB					; save B (data)
					; setup
	LDX	#REGBS				; ensure X is correct
	LDY	#EXBUF2				; RX buffer address
	BCLR	PORTD,X,EXPDATO			; ensure TX data output is clear
	BSET	PORTD,X,EXPCLK			; ensure clock is clear
	CLR	EXB2CK				; preset checksum
	LDAA	#0FFH				; initial byte count
	STAA	EXB2BC				;  "
	LDAA	#08D				; load bit counter
					; loop start, set clock & wait
IRQRX71	BCLR	PORTD,X,EXPCLK			; set clock
	LDAB	#40D				; \
IRQRX72	DECB					;  > bit setup delay
	BNE	IRQRX72				; /
					; save data bit
	LDAB	0,Y				; get current data byte
	BRSET	PORTD,X,EXPDATI,IRQRX73		; \   test RX data bit (inverted)
	SEC					;  >   set carry
	BRA	IRQRX74				;  >  continue
IRQRX73	CLC					; /    clear carry
IRQRX74	ROLB					; rotate carry in
	STAB	0,Y				; save current data byte
	STAB	EXB2LB				; save for byte count
	BSET	PORTD,X,EXPCLK			; clear clock
	LDAB	#10D				; \
IRQRX75	DECB					;  > bit gap delay
	BNE	IRQRX75				; /
					; next bit
	DECA					; update bit counter
	BNE	IRQRX71				; loop (same byte)
					; next byte
	LDAB	EXB2LB				; get last byte received
	ADDB	EXB2CK				; add to checksum
	STAB	EXB2CK				;  save checksum
	INY					; next buffer address
	CPY	#EXBUF3-3			; check for overflow
	BEQ	IRQRX82				;  yes, finish/cancel RX
	LDAA	EXB2BC				; \
	DECA					;  > byte counter
	STAA	EXB2BC				; /
	BEQ	IRQRX80				; finished
	CMPA	#0FFH-4D			; byte count in message ?
	BNE	IRQRX78				;  no, skip
	LDAB	EXB2LB				; get last byte received
	DECB					; \
	DECB					;  > adjust byte count
	DECB					;  >  & save
	STAB	EXB2BC				; /
IRQRX78	LDAA	#08D				; reset bit counter
	BRA	IRQRX71				; loop (new byte)
					; test checksum
IRQRX80	LDAA	EXB2CK				; test checksum
	BEQ	IRQRX81				;  pass
	BSET	EXPFLG1,01000000B		; flag error
	BSET	EXPFLG1,00001000B		; flag new message received
	BRA	IRQRX83				;  continue
IRQRX81	BCLR	EXPFLG1,01100000B		; flag no error
	BSET	EXPFLG1,00001000B		; flag new message received
	BRA	IRQRX83				;  continue
					; finish with error
IRQRX82	BSET	EXPFLG1,00100000B		; flag error
	BSET	EXPFLG1,00100000B		; flag error
					; finish
IRQRX83	BCLR	PORTD,X,EXPCLK			; set clock
	LDAB	#10D				; \
IRQRX84	DECB					;  > +1 last clock pulse
	BNE	IRQRX84				; /
	BSET	PORTD,X,EXPCLK			; clear clock
;	BCLR	PORTD,X,EXPDATO			; clear TX data output
	BSET	EXPFLG1,10000000B		; flag new message
	PULB					; restore B (data)
	PULA					; restore A
	PULX					; restore X
	RTI					; finished

;************************************************************************
;************************************************************************
;*****; UTILITIES ; UTILITIES ; UTILITIES ; UTILITIES ; UTILITIES *******
;*****; UTILITIES ; UTILITIES ; UTILITIES ; UTILITIES ; UTILITIES *******
;************************************************************************
;************************************************************************
; LOOP BASED DELAY

; Call with time in "Y"

DELAY1	PSHX				; save 1
DE13	LDX	#14D6H			; 16mS time
DE12	DEX				;
	BNE	DE12			;
	DEY				;
	BNE	DE13			;
	PULX				; restore 1
	RTS				; finished

;------------------------------------------------------------------------
;------------------------------------------------------------------------
;	LCD MESSAGES ( LCDMSG )
;------------------------------------------------------------------------
;------------------------------------------------------------------------

; example message send call

;	LDY	#IOM1				; message ID (address)
;	JSR	IOTXPM				;  send message to LCD

;------------------------------
; Pre-Defined messages:

; IOM10	=	clear the display
; IOM11	=	start of line 1
; IOM12	=	start of line 2
; IOM51	=	"application message"
; IOM52	=	"application message"
; IOM54	=	"debug message"

; NOTE: maximum message length is 20 data bytes.

;------------------------------
; LCD CONTROL MESSAGES FOLLOW
;------------------------------
; CLEAR LCD

IOM10	DFB	IOM10_E-IOM10-1		; byte count
	DFB	21H			; id		KDC1
	DFB	00H			; to		all units of ID 21
	DFB	UID			; from		the master
	DFB	IOM10_E-IOM10-1		; byte count
	DFB	0D3H			; command	clear display
IOM10_E	DFB	00H			; checksum

;------------------------------
; Line 1

IOM11	DFB	IOM11_E-IOM11-1		; byte count
	DFB	21H			; id		KDC1
	DFB	00H			; to		all units of ID 21
	DFB	UID			; from		the master
	DFB	IOM11_E-IOM11-1		; byte count
	DFB	0D5H			; command	set address
	DFB	00H			; data		address
IOM11_E	DFB	00H			; checksum

;------------------------------
; Line 2

IOM12	DFB	IOM12_E-IOM12-1		; byte count
	DFB	21H			; id		KDC1
	DFB	00H			; to		all units of ID 21
	DFB	UID			; from		the master
	DFB	IOM12_E-IOM12-1		; byte count
	DFB	0D5H			; command	set address
	DFB	40H			; data		address
IOM12_E	DFB	00H			; checksum

;------------------------------
; TEXT MESSAGES FOLLOW
;------------------------------
; message

IOM51	DFB	IOM51_E-IOM51-1		; byte count
	DFB	21H			; id		KDC1
	DFB	00H			; to		all units of ID 21
	DFB	UID			; from		the master
	DFB	IOM51_E-IOM51-1		; byte count
	DFB	0D7H			; command	write data to display
	DFB	" project code start "	; data		message body
IOM51_E	DFB	00H			; checksum

;------------------------------
; message

IOM52	DFB	IOM52_E-IOM52-1		; byte count
	DFB	21H			; id		KDC1
	DFB	00H			; to		all units of ID 21
	DFB	UID			; from		the master
	DFB	IOM52_E-IOM52-1		; byte count
	DFB	0D7H			; command	write data to display
	DFB	" It Works !! no ??? "	; data		message body
IOM52_E	DFB	00H			; checksum

;------------------------------
; message

IOM54	DFB	IOM54_E-IOM54-1		; byte count
	DFB	21H			; id		KDC1
	DFB	00H			; to		all units of ID 21
	DFB	UID			; from		the master
	DFB	IOM54_E-IOM54-1		; byte count
	DFB	0D7H			; command	write data to display
	DFB	"debug msg. #1       "	; data		message body
IOM54_E	DFB	00H			; checksum

;------------------------------------------------------------------------
;------------------------------------------------------------------------
; copyright notice

	DFB	"GPC_5A1 V0.1 11 MAR 2001  "
	DFB	"PAUL M BEALING  "
	DFB	"(C) 2001 PMB  "

;************************************************************************
;************************************************************************
;************************************************************************
;************************************************************************
;************************************************************************

	END